Serial interfaces for data communications between components of data processing systems are numerous. One fairly typical such interface definition is referred to as the SPI (Serial Peripheral Interface) and is incorporated in many microcomputers and peripherals designed by Motorola, Inc. of Austin, Texas.
FIG. 1 illustrates the SPI, which may be characterized as a synchronous, three-wire serial interface. A master device 10, such as a microcomputer (MCU), and a slave device 11, such as an analog-to-digital converter or similar peripheral, communicate by means of their respective SPI interfaces. In master device 10, the SPI apparatus comprises a master shift register 12 and a clock generator 13. The least significant bit of shift register 12 has an input connected to a pin labeled MISO (master in/slave out) and the most significant bit of shift register 12 has an output connected to a pin labeled MOSI (master out/slave in). The output of clock generator 13 is connected to the clock input of shift register 12 and to a pin labeled SCK (for S clock).
The SPI apparatus of slave device 11 (there may, of course, be more than one slave device coupled to a single master) comprises a slave shift register 15. A least significant bit of shift register 15 has an input connected to a pin labeled MOSI and a most significant bit of shift register 15 has an output connected to a pin labeled MISO. The clock input of shift register 15 is connected to a pin labeled SCK.
The respective MOSI, MISO and SCK pins of master device 10 and slave device 11 are connected to one another. In addition, one or more chip select signals of master device 10 are connected to enable inputs of slave device 11. Both master device 10 and slave device 11 have a data path for entering data to be transmitted into and retrieving received data from their respective shift registers. In addition, both typically have status register bits for indicating the current status of the interface and control register bits for configuring the interface.
The primary drawback of the SPI interface as described above is that it requires a relatively high degree of intervention from the controller of the master device (typically the central processing unit (CPU) of an MCU), which is often subject to servicing demands from many different sub-systems in addition to the SPI interface. A single data transfer is limited to the number of bits which can be held in the SPI shift register, typically 8. Every time a data transfer is to be commenced, the CPU must write the byte to be transferred to the shift register and assert a control bit to commence the serial transfer (or, equivalently, assert the control bit then read the received byte when the transfer is complete). Typically, when a serial transfer is complete, the SPI interrupts the CPU to demand further service, for instance, the loading of a new byte of data for transmission. Alternatively the CPU may continually poll the SPI to determine if service is required. In either case, the required CPU intervention for each byte transferred is substantial and the frequency with which the CPU must dedicate its resources to servicing the SPI is high.